This skill guides Claude to design schematics using Konnect MCP tools.\nALL modifications go through MCP tools — never edit .kicad_sch files directly.
\nBefore any schematic work, load the required toolsets:
\nload_toolset('sch_components') # place, move, rotate, delete symbols\nload_toolset('sch_wiring') # wires, net labels, power symbols, connections\nload_toolset('sch_analysis') # connection validation, short and orphan checks\nload_toolset('sch_export') # direct ERC and rendered schematic evidence\nload_toolset('project') # save_project before formal checks\nLoad additional toolsets as needed:
\nload_toolset('library') # search_symbols, get_symbol_info, list_symbol_libraries\nload_toolset('sch_batch') # batch operations for 3+ items\nAlways call get_active_toolsets() first to see what is already loaded.
Read references/common-lib-ids.md when choosing\na common generic KiCad symbol. It is a quick-start index, not an allowlist;\nsearch the active libraries when the required part is absent or package-specific.
search_symbols to find the correct lib_idget_symbol_info to see pin names, numbers, and positionslist_schematic_componentsBefore placing or wiring a custom symbol, a manufacturer-specific discrete,\nor any package whose view can be mirrored, require the kicad-library skill's\naccepted physical pin map for the exact MPN and package suffix. The map must\njoin each datasheet lead to the symbol pin and footprint pad, identify the\ndrawing view/direction, reconcile duplicate and mechanical pads, and include\nquery-back plus disposable rendered inspection. get_symbol_info proves the\nlibrary data that exists; it does not prove that data matches the package.
If the accepted physical pin map is missing, incomplete, based on a different\nsuffix, or ambiguous about top/bottom/mating view, stop before real schematic\nplacement. Do not infer physical numbering from a generic symbol name or from\nthe order pins appear on screen.
\n| Component | \nlib_id | \n
|---|---|
| Resistor | \nDevice:R | \n
| Capacitor | \nDevice:C | \n
| Capacitor Polar | \nDevice:C_Polarized | \n
| Inductor | \nDevice:L | \n
| LED | \nDevice:LED | \n
| Diode | \nDevice:D | \n
| Zener | \nDevice:D_Zener | \n
| NPN Transistor | \nTransistor_BJT:Q_NPN_BEC | \n
| PNP Transistor | \nTransistor_BJT:Q_PNP_BEC | \n
| N-MOSFET | \nTransistor_FET:Q_NMOS_GDS | \n
| P-MOSFET | \nTransistor_FET:Q_PMOS_GDS | \n
| 2-pin Connector | \nConnector_Generic:Conn_01x02 | \n
| 4-pin Connector | \nConnector_Generic:Conn_01x04 | \n
| Ground | \npower:GND | \n
| +3.3V | \npower:+3V3 | \n
| +5V | \npower:+5V | \n
| VCC | \npower:VCC | \n
| VDD | \npower:VDD | \n
Power symbols: GND uses 0 (arrow points down), VCC/VDD/+3V3/+5V use 0 (arrow points up).
\nRead references/wiring-patterns.md when\nchoosing between direct wires and labels or when building one of its common\nsubcircuits. Verify every named pin against the placed symbol before applying a\npattern.
| Scenario | \nMethod | \nWhy | \n
|---|---|---|
| Two pins physically close (<30mm) | \nconnect_pins | \nDirect wire, auto-routed | \n
| Named signal (SDA, MOSI, EN, etc.) | \nconnect_to_net | \nStub wire + net label, cleaner | \n
| Power rail (VCC, GND, +3V3) | \nadd_power_symbol | \nProper power symbol, global net | \n
| Bus signals (D0-D7) | \nconnect_to_net | \nNet labels with bus naming | \n
| Cross-sheet signal | \nGlobal label | \nConnects across schematic sheets | \n
| Multiple pins to same net (3+) | \nbatch_connect_to_net | \nEfficient bulk operation | \n
Use for direct pin-to-pin connections. The tool auto-routes with L-bends.
\nconnect_pins(schematic, ref1, pin1, ref2, pin2)\nUse for named nets. Creates a short stub wire and attaches a net label.
\nconnect_to_net(schematic, reference, pin_number, net)\npin_x/pin_y: the stub then points away\nfrom the symbol body on its own, instead of the label text running back\nacross the pin names. Override with direction only to fix a layout clash.batch_connect_to_net does the same for many pins in one read/write, and\nplaces its labels directly on the pin endpoints without stubs.add_schematic_net_label instead? Take its\nrotation from orientation_degrees in get_schematic_pin_locations, or the\ntext reads back across the symbol's pin names.Use for all power connections, in preference to labelling a pin with the rail name.
\nadd_power_symbol(schematic, power_net, x, y, rotation?)\nget_schematic_pin_locations) — a power symbol carries its\npin at its own origin, so the two coinciding is the connection.power_net is loaded as power:<power_net>, so it must name a symbol in\nKiCad's power library: +3V3 and +12V, never 3V3 or 12V. A miss is an\nerror and nothing is placed.rotation defaults to 0 — see Rotation Conventions above.Load sch_batch toolset when placing 3 or more components or making bulk connections.
Place multiple components in one call. Provide schematic and a components array of {lib_id, x, y, rotation?, reference?, value?, unit?} objects. Pass reference explicitly for each component -- it is not auto-assigned.
Connect multiple pins to the same net in one call. Ideal for:
\nBulk-modify component properties (values, footprints, fields) across multiple components.
\nPlace 100nF cap (Device:C) within 5mm of IC power pin. Connect one pin to VCC via power symbol, other pin to GND via power symbol. One cap per VCC/VDD pin.
\nPlace resistor (Device:R) vertically. Connect one pin to the signal net via connect_to_net, other pin to VCC via add_power_symbol. Typical values: 4.7k for I2C, 10k for general.
Two resistors in series, vertically aligned. Top to input net, middle junction to output net, bottom to GND. Use connect_to_net for input/output, add_power_symbol for GND.
Resistor in series with LED. Connect resistor to signal/power, resistor to LED anode, LED cathode to GND. R = (Vsupply - Vf) / If. Typical: 330R for 3.3V, 470R for 5V.
\nFor analog circuits: 100nF ceramic + 10uF electrolytic in parallel, close to power pins. Place ceramic closest to IC.
\nCrystal (Device:Crystal) between XI and XO pins. Two load capacitors from each crystal pin to GND. Typical load caps: 12-22pF. Optional 1M feedback resistor across crystal.
\nAfter placing components and wiring, always run these checks:
\nAssigns reference designators (R1, C1, U1, etc.) to all unannotated components. Run after all placement is complete.
\nChecks that all wires connect properly to pins. Reports:
\nVerifies that components have the expected connections. Reports:
\nFinds floating wires, labels, and symbols that are not connected to anything.
\nannotate_schematic, then save with save_project.validate_wire_connections and validate_component_connections.find_shorted_nets; reconcile each finding against the intended nets.find_orphan_items as a heuristic and corroborate its findings.run_erc and classify every violation.render_schematic_png with inline output and inspect the actual image.The agent can see its own schematic. After meaningful edits:
\nrender_schematic_png — rasterize the sheet (pass inline true to get\nthe image back as base64 and actually look at it).set_visual_baseline — capture the known-good render before a batch of\nedits (stored under the project's own state directory with the source\nhash and renderer identity).compare_visual_baseline — after edits: PASS/DRIFT against a 2% content\nthreshold with the changed region's bounding box. \"No baseline stored\" is\na normal state, and a baseline from an older renderer is flagged rather\nthan silently trusted.Use the loop to catch what connectivity checks cannot. Completion requires\ncoherent functional grouping, label-inclusive overlap inspection, clear signal\nflow, and page-boundary acceptance for every symbol, label, and note. Inspect\nthe image itself; a successful render command is not visual acceptance.
\nApply this order when evidence disagrees:
\nA weaker heuristic may raise a question but does not override stronger direct\nevidence. If any required check did not run, failed structurally, returned\nimpossible coverage, or contradicts stronger evidence without resolution, the\nresult is INCOMPLETE. Report the blocked evidence and stop short of a clean or\nproduction-ready claim.
get_schematic_pin_locations or get_symbol_info to look up pin numbers before connectingsearch_symbols to confirm lib_id existsadd_power_symbol for rails, not net labelssave_project after major operationsget_active_toolsets() and load what you need before starting