| Field | \nBound contract | \n
|---|---|
| Trigger | \nFirmware never reaches main(), a new MCU is being brought up without a vendor HAL, or a custom startup.s, Reset_Handler, or crt0 is being written or debugged on Cortex-M or RISC-V. | \n
| Authority | \nRead-only: emits startup code, linker symbol requirements, and diagnostics to chat; the user places them in the project. Rollback is not needed because no file is written. No remote mutation. | \n
| Side effect | \nChat output only. | \n
| Done | \nThe startup path from the reset vector to main() is stated step by step, the vector table layout and the .data and .bss loops are given for the target core, and every linker symbol the code uses is listed with the linker script line that defines it. | \n
MEMORY regions and the symbols it exports.State the boot sequence for the core before writing code. On Cortex-M the hardware loads SP from vector 0 and branches to vector 1, Reset_Handler. On RISC-V the core starts at the reset address with sp undefined, so the first instruction sets it. Done when: the sequence is written as an ordered list from power-on to main().
Cortex-M vector table head:
\n| Index | \nEntry | \n
|---|---|
| 0 | \nInitial stack pointer (_estack) | \n
| 1 | \nReset_Handler | \n
| 2 | \nNMI_Handler | \n
| 3 | \nHardFault_Handler | \n
| 4 and up | \nFault handlers, then device IRQ handlers in NVIC order | \n
Write the vector table and Reset_Handler for Cortex-M. Copy .data from its load address in flash to its run address in RAM, zero .bss, then call SystemInit and main. Compare addresses with an unsigned branch (bcc), because addresses are unsigned. Done when: the assembly assembles for the target and the three symbol pairs come from the linker script.
.syntax unified\n.thumb\n\n.section .isr_vector,\"a\",%progbits\n.global g_pfnVectors\ng_pfnVectors:\n .word _estack\n .word Reset_Handler\n .word NMI_Handler\n .word HardFault_Handler\n /* remaining fault and device IRQ vectors from the vendor CMSIS header order */\n\n.section .text.Reset_Handler\n.thumb_func\n.global Reset_Handler\nReset_Handler:\n ldr r0, =_sidata /* .data load address in flash */\n ldr r1, =_sdata /* .data run address in RAM */\n ldr r2, =_edata\n b copy_check\ncopy_data:\n ldr r3, [r0], #4\n str r3, [r1], #4\ncopy_check:\n cmp r1, r2\n bcc copy_data\n ldr r2, =_sbss\n ldr r4, =_ebss\n movs r3, #0\n b zero_check\nzero_bss:\n str r3, [r2], #4\nzero_check:\n cmp r2, r4\n bcc zero_bss\n bl SystemInit\n bl main\n b .\nDefine the linker symbols the startup code names. _estack is the top of RAM, _sidata is the load address of .data, and _sdata, _edata, _sbss, _ebss bracket the sections. Done when: each symbol appears in the linker script and .data carries AT> FLASH so its load and run addresses differ.
_estack = ORIGIN(RAM) + LENGTH(RAM);\n_sidata = LOADADDR(.data);\nRelocate the vector table when the image does not sit at the default boot address. Write SCB->VTOR, then __DSB() and __ISB(). The table base must be aligned to its own size rounded up to a power of two, with a minimum of 128 bytes on ARMv7-M; the mask below is the ARMv7-M TBLOFF field and a table with many vectors needs coarser alignment. Done when: VTOR holds the address of this image's g_pfnVectors and an interrupt reaches this image's handler.
void relocate_vector_table(uint32_t base)\n{\n SCB->VTOR = base & 0xFFFFFF80U; /* ARMv7-M TBLOFF field; align to table size */\n __DSB();\n __ISB();\n}\nWrite the RISC-V entry when the target is RISC-V. Set sp, zero .bss with sw on RV32 or sd on RV64, set mtvec to the trap handler, and call main. Done when: the entry assembles for the target XLEN and mtvec points at a valid handler before interrupts are enabled.
.section .text.entry\n.global _start\n_start:\n la sp, _stack_top\n la t0, _bss_start\n la t1, _bss_end\nclear_bss:\n beq t0, t1, bss_done\n sw zero, 0(t0) /* sd on RV64 */\n addi t0, t0, 4 /* 8 on RV64 */\n j clear_bss\nbss_done:\n la t0, trap_handler\n csrw mtvec, t0\n call main\n j .\nAssign the remaining crt0 duties and confirm who owns each. Done when: every row below has an owner in the project.
\n| Task | \nOwner | \n
|---|---|
Copy .data from flash to RAM | \nReset_Handler | \n
Zero .bss | \nReset_Handler | \n
| Initial stack | \nVector 0 on Cortex-M; explicit sp load on RISC-V | \n
Heap (_sbrk) | \nOptional; newlib syscall or a custom allocator | \n
| C++ static constructors | \n__libc_init_array() from newlib, called before main | \n
| FPU enable on Cortex-M4F and M7 | \nSystemInit, by writing SCB->CPACR to grant CP10 and CP11 full access before any float instruction | \n
Keep main from returning. The b . after bl main catches a return; the body of main normally ends in a loop or __WFI(). Done when: a return from main lands in a known loop and not in the next bytes of flash.
Verify on the target: halt at Reset_Handler with the debugger, step the copy and zero loops, and inspect a known initialized global and a known zero global at the first line of main. Done when: both globals hold their expected values.
| Symptom | \nCause | \nFix | \n
|---|---|---|
| HardFault on the first instruction | \nVector 0 does not point into RAM | \nSet _estack to ORIGIN(RAM) + LENGTH(RAM). | \n
| Initialized globals read as garbage | \n.data never copied | \nAdd the copy loop and define _sidata with LOADADDR(.data). | \n
| Zero-initialized globals are non-zero | \n.bss never zeroed | \nAdd the zero loop over _sbss to _ebss. | \n
| Interrupts run the wrong handler or fault | \nVTOR points at another image's table | \nWrite SCB->VTOR to this image's table and issue __DSB(); __ISB();. | \n
| Crash on the first float instruction | \nFPU not enabled on M4F or M7 | \nSet CP10 and CP11 in SCB->CPACR in SystemInit. | \n
C++ constructor crashes before main | \nConstructors ran before clocks or peripherals were ready | \nCall SystemInit before __libc_init_array. | \n
Execution falls off the end of main | \nNo loop after main | \nLoop or __WFI() in main; keep b . after the call. | \n
Startup code for the target core (vector table, Reset_Handler or _start, .data and .bss loops), the list of linker symbols it requires with their defining lines, the VTOR relocation routine when the image is offset, and a debugger checklist for confirming globals at the first line of main.