RISC-V is a small load-store ISA grown through named extensions. This skill covers user-mode RV32 and RV64 assembly, the psABI register contract, and the QEMU loop.
\n| Field | \nBound contract | \n
|---|---|
| Trigger | \nThe task writes inline asm or assembly for RV32 or RV64, decodes ABI register names, names an ISA extension string, enables compressed instructions, or debugs RISC-V under QEMU with GDB. | \n
| Authority | \nRead-only. The skill explains and drafts; edits land through the normal coding path. No remote mutation. | \n
| Side effect | \nNone. | \n
| Done | \nThe drafted assembly assembles for the named base ISA and extensions, or the compiler output under discussion is explained register by register. | \n
-march string such as rv64gc, written IMAFDC in ISA order.virt for user or system work, hardware otherwise.| Register | \nABI name | \nRole | \n
|---|---|---|
x0 | \nzero | \nHardwired zero, writes are discarded | \n
x1 | \nra | \nReturn address | \n
x2 | \nsp | \nStack pointer | \n
x3 | \ngp | \nGlobal pointer | \n
x4 | \ntp | \nThread pointer | \n
x5 to x7, x28 to x31 | \nt0 to t6 | \nTemporaries, caller saved | \n
x8 | \ns0/fp | \nFrame pointer or saved register, callee saved | \n
x9, x18 to x27 | \ns1, s2 to s11 | \nSaved registers, callee saved | \n
x10 to x17 | \na0 to a7 | \nArguments and return values, caller saved | \n
f0 to f7, f28 to f31 | \nft0 to ft11 | \nFP temporaries, caller saved | \n
f8 to f9, f18 to f27 | \nfs0 to fs11 | \nFP saved, callee saved | \n
f10 to f17 | \nfa0 to fa7 | \nFP arguments and returns, caller saved | \n
Write the calling convention into the code. Args go in a0 to a7, extra args on the stack, return value in a0. Save callee-saved registers before use and restore them before return. Done when: any s register used is saved and restored.
Read the base instructions. Done when: each instruction in the fragment parses.
\nadd a0, a1, a2 # a0 = a1 + a2\nsub a0, a1, a2\nmul a0, a1, a2 # M extension\ndiv a0, a1, a2 # signed divide, remainder in rem\nand a0, a1, a2\nor a0, a1, a2\nxor a0, a1, a2\nsll a0, a1, a2 # shift left by register\nslli a0, a1, 3 # shift by immediate\nlw a0, 0(a1) # load word, RV32\nld a0, 0(a1) # load doubleword, RV64\nlbu a0, 0(a1) # byte, zero-extended\nsw a0, 0(a1)\nsd a0, 0(a1)\nbeq a0, a1, label # branch if equal\nblt a0, a1, label # signed less than\nbge a0, a1, label # unsigned forms are bgeu/bltu with the u suffix\njal ra, func # call\njalr zero, ra, 0 # return, pseudo for ret\nla a0, symbol # load address, pseudo\nli a0, 42 # load immediate, pseudo\n.global factorial # RV64 example\nfactorial:\n li a1, 1 # result accumulator\n1: beqz a0, 2f\n mul a1, a1, a0\n addi a0, a0, -1\n j 1b\n2: mv a0, a1\n ret\nName the ISA correctly. Extensions combine into one string in fixed order. rv64gc is the common application profile and expands to IMAFDC plus Zicsr and Zifencei. a brings atomics, m integer multiply and divide, f and d single and double float. Done when: the -march string matches the hardware or QEMU target.
Write inline asm with the right constraints. RISC-V CSR access needs csrr or the csrrs family, and a memory clobber when the instruction has memory side effects. Done when: inputs, outputs, and clobbers are each listed.
static inline uint64_t rdcycle(void) {\n uint64_t val;\n __asm__ volatile(\"rdcycle %0\" : \"=r\"(val));\n return val;\n}\n-march=rv64gc or disable with -march=rv64ima. Verify with disassembly: compressed instructions print as c.addi, c.ld, and their c. family. Done when: the disassembly shows the intended encoding width.riscv64-linux-gnu-gcc -march=rv64gc -O2 prog.c -o prog\nriscv64-linux-gnu-objdump -d prog | grep -E '\\sc\\.'\nqemu-riscv64 -g 1234 ./prog # user mode\nqemu-system-riscv64 -M virt -nographic -kernel fw_jump.elf -gdb tcp::1234 -S\nriscv64-linux-gnu-gdb ./prog\n(gdb) target remote :1234\n(gdb) b main\n(gdb) c\n| Failure class | \nBehavior | \n
|---|---|
f instructions fail to assemble | \nThe -march string lacks f or d. Extend it, for example rv64gc already carries both. | \n
| Atomics undefined | \nThe a extension is missing from -march, or the target truly lacks it. Add a or rewrite with a lock. | \n
| Corruption across a call | \nA callee-saved s register was used without save and restore. Audit the prologue and epilogue. | \n
| QEMU hangs at boot | \nThe kernel or firmware image does not match the machine. Re-run with -nographic and read the early console output. | \n
| GDB cannot connect | \nThe port disagrees or QEMU lacks -g. Check the QEMU command line first, then the GDB target. | \n
Annotated assembly or inline asm with register roles, the exact -march string, and for QEMU work the exact launch and GDB commands. The full psABI table, including the floating-point calling variants, is in references/riscv-abi.md.